CMOS logic circuits consume static power when the circuit is inactive. In one prior technique, a static power reduction technique allows unused portions of a circuit to be turned off when the circuit is inactive to save power. However, disconnecting the circuit from the supply also results in a loss of the logic state that is preserved in latches/flip-flop storage elements.
Another prior technique uses volatile latch circuits cooperating with non-volatile latch circuits to store the logic state of the volatile latch circuit. These shadow non-volatile latches require additional circuitry and add dynamic power during normal operation.
In CMOS standard cell based and gate-array integrated circuits, providing multiple supplies of different voltage potential may be needed for biasing the substrate and/or Nwell potential separately from the device source potential(s). A possible solution is by routing multiple supplies carrying distinctly different voltage potentials within each cell boundary on the first metal routing layer (M1). However, this solution consumes lots of area on a chip since 1) the power supply wiring, 2) the cell connection and 3) the signaling wiring all use the same routing layer. Further, the routing of power supply lines entirely in the first metal layer causes cell wiring to be excluded from the regions of the cell where those power supply wiring are routed. The cell wiring is excluded from the regions of the cell regardless of whether or not that voltage supply wiring is used by the specific cell because the power traces on the Ml layer extend into the macro cell and occupy area that would have been available for cell and signaling routing.